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INTEGRATED CIRCUITS
DATA SHEET
TZA3014 2.5 Gbits/s postamplifier with level detector
Product specification Supersedes data of 2000 Aug 09 File under Integrated Circuits, IC19 2001 Jun 25
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
FEATURES * Single 3.3 V power supply * Wideband operation from 50 kHz to 2.5 GHz (typical value) * Fully differential * On-chip DC-offset compensation without external capacitor * Interfacing with supplied positive or negative logic * Positive Emitter Coupled Logic (PECL) or Current-Mode Logic (CML) compatible data outputs adjustable from 200 to 800 mV (p-p) single-ended * Power-down capability for unused output or detector * Rise and fall times of 80 ps (typical value) * Inverted output possible * Input level detection circuit for Received Signal Strength Indicator (RSSI) and Loss Of Signal (LOS), programmable from 0.4 to 400 mV (p-p) single-ended, with open-drain comparator output for directly interfacing positive or negative logic * Reference voltage for output level and LOS adjustment * HTQFP32 and HBCC32 plastic packages with exposed pad * Mute input. ORDERING INFORMATION TYPE NUMBER TZA3014HT TZA3014VH TZA3014U PACKAGE NAME HTQFP32 HBCC32 - DESCRIPTION plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm APPLICATIONS
TZA3014
* Postamplifier for SDH/SONET transponder * SDH/SONET wavelength converter * PECL driver * Fibre channel arbitrated loop * Signal level detectors * Swing converter CML 200 mV (p-p) to PECL 800 mV (p-p) * 2.5 GHz clock amplification. GENERAL DESCRIPTION The TZA3014 is a low gain postamplifier with a LOS detector and a RSSI designed for use in critical signal path control applications, such as loop-through or Wavelength Division Multiplexing (WDM). The signal path is capable of operating from 50 kHz up to 2.5 GHz. The TZA3014 can be delivered in HTQFP32 and HBCC32 packages and as bare die.
VERSION SOT547-2 SOT560-1 -
plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm bare die; 2.22 x 2.22 x 0.28 mm
2001 Jun 25
2
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
BLOCK DIAGRAM
TZA3014
handbook, full pagewidth
GNDA LOSTH
32 (40) 10 (12)
disable LOS output comparator
(31) 25
GNDB
RSSI 1x offset compensation
5 k
(35) 27 (34) 26
LOS RSSI
offset compensation
LEVEL INV VCCA IN INQ VCCA TEST MUTE
12 (15) 29 (37) 1 2 3 4 cross-over switch
level
(30) 24 (29) 23 (28) 22 buffer amplifier (27) 21
VCCB OUT OUTQ VCCB
15 (19) 31 (39)
TZA3014
BAND GAP REFERENCE
(17) 14
Vref
MGU122
The numbers in parentheses refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
2001 Jun 25
3
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
PINNING SYMBOL VCCA IN INQ VCCA n.c. n.c. n.c. n.c. n.c. n.c. n.c. LOSTH PIN 1 2 3 4 - - 5 6 7 8 9 10 PAD 1 2 3 4 5 6 7 8 9 10 11 12 TYPE(1) S I I S - - - I I S S I DESCRIPTION supply voltage for input and LOS detector
TZA3014
differential input; complimentary to pin INQ; DC bias level is set internally at approximately VCC - 0.33 V differential input; complimentary to pin IN; DC bias level is set internally at approximately VCC - 0.33 V supply voltage for input and LOS detector not connected not connected not connected not connected not connected not connected not connected input for setting threshold level of LOS detector; threshold level is set by connecting external resistors between pins VCCA and Vref; when forced to GNDA or not connected, the LOS detector is switched off not connected not connected input for setting AC level of the output circuit; output signal level is set by connecting external resistors between pins VCCA and Vref; when forced to VCCA or not connected, pins OUT and OUTQ will be switched off not connected reference voltage for programming output level circuit and LOS threshold; typical value is VCC - 1.6 V; no external capacitor allowed not connected for test purposes only; to be left open-circuit in the application not connected not connected not connected not connected not connected not connected not connected supply voltage for output circuit PECL or CML compatible differential output; complimentary to pin OUT PECL or CML compatible differential output; complimentary to pin OUTQ supply voltage for output circuit ground for output circuit not connected
n.c. n.c. LEVEL
11 - 12
13 14 15
I - I
n.c. Vref n.c. TEST n.c. n.c. n.c. n.c. n.c. n.c. n.c. VCCB OUTQ OUT VCCB GNDB n.c. n.c.
13 14 - 15 16 17 18 19 20 - - 21 22 23 24 25 - -
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
I O - I S S O O S - - S O O S S O
O-DRN not connected
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
SYMBOL RSSI LOS n.c. INV n.c. MUTE GNDA GNDp Note
PIN 26 27 28 29 30 31 32 pad
PAD 34 35 36 37 38 39 40 -
TYPE(1) O RSSI output
DESCRIPTION
O-DRN output of LOS detector; direct drive to either positive or negative supplied logic via internal 5 k resistor TTL TTL TTL TTL S S not connected input to invert the signal at pins OUT and OUTQ; supports positive or negative logic not connected input to mute the output signal on pins OUT (`0') and OUTQ (`1'); supports positive or negative logic ground for input and LOS detector ground pad (exposed die pad)
1. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.
VCCA IN INQ VCCA n.c. n.c. n.c. n.c.
1 2 3 4 exposed pad
27 LOS
29 INV
30 n.c.
28 n.c.
handbook, full pagewidth
25 GNDB
32 GNDA
31 MUTE
26 RSSI
24 VCCB 23 OUT 22 OUTQ 21 VCCB 20 n.c. 19 n.c. GNDp 18 n.c. 17 n.c.
TZA3014HT
5 6 7 8
LOSTH 10
n.c. 11
LEVEL 12
n.c. 13
Vref 14
TEST 15
n.c. 16
n.c. 9
MGU123
Fig.2 Pin configuration HTQFP32 package.
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
GNDA
MUTE
VCCA IN INQ VCCA n.c. n.c. n.c. n.c.
1 2 3 4 5 6 7 8 9
n.c.
32
31 30
29
28
27
LOS
RSSI
handbook, full pagewidth
26
25 24 23 22 VCCB OUT OUTQ VCCB n.c. n.c. n.c. n.c.
exposed pad
TZA3014VH
21 20 19 GNDp 18 16
n.c.
10
LOSTH
11 12
n.c. LEVEL
13
n.c.
14
Vref
15
TEST
17
GNDB
MGU124
Fig.3 Pin configuration HBCC32 package.
2001 Jun 25
6
INV
n.c.
n.c.
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
FUNCTIONAL DESCRIPTION The TZA3014 is a postamplifier with a RSSI circuit to provide output signals for RSSI and LOS (see Fig.1). The input signal can be amplified to a programmable level. An active level control circuit ensures this level. The control voltage on pin INV inverts the outputs, so avoiding a required complicated Printed Circuit Board (PCB) layout. An offset compensation circuit minimizes the effect of any voltage offset present at the input. The RSSI and LOS detector are based on a 7-stage `successive detection' circuit which provides a logarithmic output. The LOS detector is followed by a comparator with a programmable threshold. The input signal level detection is implemented to check if the input signal is above the user-programmed level. The user can ensure that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. A second offset compensation circuit minimizes the effect of any voltage offset present in the logarithmic amplifier. RF input circuit The input circuit contains internal 50 resistors decoupled to VCCA via an internal common mode 12 pF capacitor (see Fig.4). The inputs IN and INQ are DC-biased at approximately VCCA - 0.33 V by an internal reference generator. The TZA3014 can be DC-coupled, but AC coupling is preferred. When DC-coupled, the drive source must operate within the allowable input range (VCCA - 1.0 V to VCCA + 0.3 V). The DC-offset voltage should stay below a few millivolts since the internal DC-offset compensation circuit has a limited correction range. When AC-coupled, do not use capacitors that cause a 3 dB cut-off point at 50 kHz (postamplifier cut-off point) or at 1 MHz (RSSI cut-off point). RF output circuit Matching the outputs of the postamplifier (see Fig.5) is not mandatory. In most applications, the receiving end of the transmission line will be properly matched, causing very few reflections. Matching the transmitting end of the transmission line to absorb reflections only, is recommended for very sensitive applications. In such cases, 100 pull-up resistors should be connected to VCCB and pins OUT and OUTQ as close as possible to the IC. However, for most applications these matching resistors are not required.
handbook, halfpage
TZA3014
VCCA 12 pF 420
50 IN INQ
50
GNDA
MGU125
Fig.4 RF input circuit.
RF output level adjustment The output level can be made compatible with CML or PECL by adjusting the voltage on pin LEVEL. The DC voltages on pins OUT and OUTQ relate to the DC voltage on pin LEVEL. Due to the effect of the 50 load resistance at the receiving end, for a given peak-to-peak value on pins OUT and OUTQ, a different voltage is required on pin LEVEL in case the output is AC-coupled and when the output is DC-coupled (see Figs 5 and 6). When pin LEVEL is not connected or connected to VCCA, the postamplifier is in power-down state (see Fig.5). DC-offset compensation loop A DC-offset compensation loop connected between the amplifier output and the buffer input maintains the toggle point at the buffer input when there is no input signal (see Fig.1). This active control circuit is integrated and does not require an external capacitor. The loop time constant determines the lower cut-off frequency of the amplifier chain, and is internally fixed at approximately 5 kHz.
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
handbook, full pagewidth
VCCA 4 R1 100
(27) 21 VCCB 100 (29) 23 OUT (28) 22 OUTQ Vo 50 50
LEVEL 12 (15) VLEVEL
Transmission lines
R2 Vref 14 (17)
REG
VCC VLEVEL Vo (V) Vo(se)(p-p)
MGU126
VLEVEL = 0.5 x Vo(se)(p-p). R1 V LEVEL = V ref x --------------------R1 + R2 VLEVEL = VCC for power-down mode. The numbers in parentheses refer to the pad numbers of the bare die version.
a. DC-coupled.
handbook, full pagewidth
VCCA 4 R1 100
(27) 21 VCCB 100 (29) 23 OUT (28) 22 OUTQ Vo 50 50
LEVEL 12 (15) VLEVEL VCC R2 Vref 14 (17) VLEVEL Vo (V) REG
Transmission lines
Vo(se)(p-p)
MGU127
VLEVEL = 1.5 x Vo(se)(p-p). R1 V LEVEL = V ref x --------------------R1 + R2 VLEVEL = VCC for power-down mode. The numbers in parentheses refer to the pad numbers of the bare die version.
b. AC-coupled. Fig.5 RF output configurations.
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
handbook, full pagewidth
MGU128
1000 Vo(se)(p-p) (mV) 800 DC-coupled 600 AC-coupled
400
200
0
0
20
40
60
100 80 VLEVEL (% of Vref)
Fig.6 Output signal as a function of VLEVEL.
TTL logic inputs MUTE and INV It should be noted that switch control voltages in positive logic are inverted in case a negative supply voltage is used (see Fig.7). Output signal as a function of inputs MUTE and INV The default logic level for inputs MUTE and INV is 0 in case these pins are not connected. See Tables 1 and 2.
Table 1
OUT and OUTQ as a function of input MUTE OUT IN `0' OUTQ INQ `1'
MUTE 0 1 Table 2
OUT and OUTQ as a function of input INV INV 0 1 OUT IN INQ OUTQ INQ IN
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
handbook, full pagewidth
logic level 1
MGS560
2.0 V
2.0 V
(1)
T TL
0.8 V 0 1.4 V GND -1 0 +1 +2 VCC +3 +4 +5 VI (V) +6 1.4 V 0.8 V
a. Positive supply voltage (VCC) and positive input voltage (VCC).
handbook, full pagewidth
logic level 1
MGS559
2.0 V
2.0 V
(1)
T TL
0.8 V 0 1.4 V VEE -4 -3 -2 -1 GND 0 +1 +2 VI (V) +3 1.4 V VCC 0.8 V
b. Negative supply voltage (VEE) and positive input voltage (VCC).
handbook, full pagewidth
logic level 1
MGS558
2.0 V
2.0 V
(1)
T TL
0.8 V 0 1.4 V VEE -4 -3 -2 -1 GND 0 +1 +2 VI (V) +3 1.4 V 0.8 V
c. Negative supply voltage (VEE) and negative input voltage (VEE).
(1) Level not defined.
Fig.7 Logic levels on pins MUTE and INV as a function of the supply voltages.
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
RSSI and LOS detection The TZA3014 monitors the level of the input AC signal. This function can prevent the output circuit from reacting to noise in case there is no valid input signal, and can ensure that only data is transmitted when there is sufficient input signal for low bit error rate system operation. The RSSI uses seven limiting amplifiers in a `successive detection' topology to closely approximate a logarithmic response over a total range of 70 dB. The AC signal is full-wave rectified by a detector at each amplifier stage. Each detector output has a current driver followed by a low-pass filter providing the first stage in the recovery of the average value of the demodulated input signal. The total current from each detector output is converted to a voltage by an internal load resistor and then buffered. When the RSSI output is used, input pin LOSTH is not to be connected to GND (standby mode). The RSSI output follows the internal 3 dB hysteresis of the LOS comparator. The LOS comparator detects when the input signal level rises above a programmable fixed threshold. Then pin LOS gets a LOW-level. The threshold level is determined by the voltage on pin LOSTH and by the level of the input AC signal (see Fig.8). A filter with a nominal time constant of 1 s prevents noise spikes from triggering the level detector. The LOS comparator has an internal 3 dB hysteresis and drives an open-drain circuit with a 5 k internal resistor allowing it to directly interface positive or negative logic circuits (see Fig.9). Its response is independent of the input signal polarity due to the circuit design and to the demodulating action of the detector which transforms the alternating input voltage to a rectified and filtered quasi DC output signal. The logarithmic voltage slope of the TZA3014 is = 1/12.5 dB/mV and mostly is independent of temperature and supply voltage due to four feedback loops in the reference circuit. The LOS detector output voltage is derived from Vref. The sensitivity of the LOS detector is affected by the RMS value of the input signal which, in its turn, depends on the frequency. VLOSTH can be calculated using the following formula: VLOSTH = VRSSI = V i(p-p) V CC + 0.458 - S RSSI x 20 log ------------------- 26E - 8 (1)
TZA3014
handbook, halfpage3 10
MGU129
Vi(se)(p-p) (mV) 102 LOS LOW-level
(1) (2)
10 LOS HIGH-level 1
(3)
10-1 10
20
30
40
50 60 70 VLOSTH (% of Vref)
VCC -0.16
VCC -0.48
VCC -0.8 VCC -1.12 VRSSI (V)
(1) PRBS pattern input signal with a frequency <1 GHz. (2) Linearity error typically 0.5 dB. (3) = 1/12.5 dB/mV.
Fig.8 Loss of signal assert level.
Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS input signal will have a VRSSI voltage of VCC - 1.013 V. If the offset voltage of the first stage increases above a certain level, the high DC gain of the amplifier circuit will cause successive stages to limit prematurely. This is prevented by the LOS detector offset control loop which extends the lower end of the amplifier's dynamic range. The offset is automatically and continuously compensated by a feedback path from the last stage. An offset at the output of the logarithmic converter is equivalent to a change of amplitude at the input. Using DC-coupling, with signal absence, and VIN not equal to VINQ (mute), the LOS detector detects full signal. Only very small signals with an average value equal to zero, can result into a zero output.
where SRSSI in [mV/dB]; VLOSTH, VRSSI and Vi(p-p) in [V].
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
handbook, halfpage
VCC 56 k LOS 5 k GNDA ILOS GND
MGU132
handbook, halfpage
GND
VCC 5.6 k LOS 5 k GNDA ILOS VEE
TZA3014
TZA3014
MGU131
a. Positive supply and positive logic.
handbook, halfpage
b. Negative supply and positive logic.
GND 56 k
TZA3014
LOS 5 k GNDA ILOS VEE
MGU130
VCC - VEE < 7 V.
c. Negative supply and negative logic. Fig.9 Loss of signal output pin LOS.
Supply current For the supply current ICCB, see Fig.10. Using a positive supply voltage Although the TZA3014 has been designed to use a single +3.3 V supply voltage (see Fig.11), some care should be taken with respect to RF transmission lines. The on-chip signals refer to the various VCC pins. The external transmission lines will most likely be referred to the pins GNDA and GNDB, being the system ground. The RF signals will change from one reference plane to another when interfacing the RF inputs and outputs. A positive supply application is very vulnerable to interference with respect to this point. For a successful +3.3 V application, special care should be taken when designing the PCB layout in order to reduce the influence of interference and to keep the positive supply voltage as clean as possible.
I CCB (mA) 60 50 40 30 20
17
(1)
10 5 0 0 0.2 0.8 0.5 Vo(se)(p-p) (V) 1
MGU133
(1) Tamb = 25 C.
Fig.10 Supply current as a function of the output voltage.
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCC Vn supply voltage DC voltage pins IN, INQ, LOSTH, LEVEL, Vref, TEST, OUTQ, OUT, GNDp, VCCA and VCCB pins LOS, INV and MUTE In DC current pins IN and INQ pins LOSTH and LEVEL pins Vref, TEST and LOS pins OUT and OUTQ pins INV and MUTE Ptot Tstg Tj Tamb total power dissipation storage temperature junction temperature ambient temperature -20 0 -1 -30 0 - -65 - -40 +20 14 +1 +30 20 0.6 +150 150 +85 -0.5 -0.5 PARAMETER MIN. -0.5
TZA3014
MAX. +5.5 V
UNIT
VCC + 0.5 V +7 V mA A mA mA A W C C C
THERMAL CHARACTERISTICS SYMBOL Rth(j-s) Rth(j-a) Rth(s-a) Rth(s-a)(req) PARAMETER thermal resistance from junction to solder point (exposed die pad) thermal resistance from junction to ambient thermal resistance from solder point to ambient (exposed die pad) required thermal resistance from solder point to ambient note 1 1s2p multi-layer test board; notes 1 and 2 1s2p multi-layer test board; notes 1 and 2 LOS detector switched on Vo = 200 mV (p-p) single-ended Vo = 800 mV (p-p) single-ended Notes 1. JEDEC standard. 2. HTQFP32 and HBCC32 packages. 130 75 K/W K/W CONDITIONS VALUE 15 33 18 UNIT K/W K/W K/W
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
CHARACTERISTICS Typical values at Tamb = 25 C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages referenced to ground; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply (pins VCCA and VCCB) VCC ICCA ICCB supply voltage supply current A supply current B LOS detector power-down LOS detector switched on amplifier power-down Vo = 200 mV (p-p) single-ended Vo = 800 mV (p-p) single-ended Ptot total power dissipation power-down Vo = 200 mV (p-p) single-ended Vo = 800 mV (p-p) single-ended TC temperature coefficient LOS detector switched on; ICCA Vo = 800 mV (p-p) single-ended; ICCB Tj Tamb VI(bias) VI Ri Ci junction temperature ambient temperature 3.13 14 24 2 11 43 60 120 250 -80 -50 -40 -40 VCC - 0.4 note 2 single-ended single-ended; note 2 VCC - 1.0 35 0.6 3.3 24 40 6 17 60 100 190 330 -50 -30 - +25 3.47 34 56 10 24 77 240 270 450 -30 -15 +125 +85 V mA mA mA mA mA mW mW mW A/K A/K C C
RF inputs in general (PECL or CML input pins IN and INQ) DC input bias voltage DC and AC input window voltage input resistance input capacitance VCC - 0.33 VCC - 0.28 V - 50 0.8 VCC + 0.3 70 1.2 V pF
Cross-over switch and postamplifier PECL OR CML INPUT PINS IN AND INQ Vi(p-p) OS(red) input voltage swing (peak-to-peak value) input offset reduction single-ended; notes 2 and 3 Vo = 200 mV (p-p) single-ended; note 4 Vo = 800 mV (p-p) single-ended; note 4 Vio(cor) input offset voltage correction range (peak-to-peak value) single-ended 50 3.8 6 -10 - 9 14 - 500 13.5 22 +10 mV dB dB mV
Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) Fn 2001 Jun 25 noise factor
Vo = 800 mV (p-p) single-ended; note 2 note 2 14
- -
75 5
170 12
V dB
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BUFFER AND AMPLIFIER Gv small signal voltage gain Vo = 200 mV (p-p) single-ended; note 5 Vo = 800 mV (p-p) single-ended; note 5 fD f-3dB(l) signal path data rate low -3 dB cut-off frequency DC compensation high -3 dB cut-off frequency propagation delay propagation delay difference total jitter crosstalk note 2 at the same signal levels; note 2 20 bits of the 28.5 kbits pattern; notes 2 and 8 note 9 50 load notes 6 and 7 note 2 9 21 - 2 15 29 2.5 5 20 34 - 10 dB dB Gbits/s kHz
f-3dB(h) tPD tPD J ct Vo(se)(p-p)
- 150 - - - 200
2.0 200 0 8 110 -
- 250 5 - - 800
GHz ps ps ps dB
PECL OR CML OUTPUTS (PINS OUT AND OUTQ) single-ended output voltage (peak-to-peak value) temperature coefficient output voltage rise time fall time output resistance output capacitance mV
TCVo tr tf Ro Co Vi Ri ta td VIL VIH Ri Ii
-1 20% to 80%; notes 6 and 8 - 80% to 20%; notes 6 and 8 - single-ended single-ended; note 2 70 0.6 VCC - Vref referenced to VCC multiplexer and inverter multiplexer and inverter 200 - - -0.3 2 100 -40
0 80 80 100 0.8 - 350
+1 - - 130 1.2
mV/K ps ps pF
LEVEL CONTROL INPUT (PIN LEVEL) input voltage input resistance VCC 600 - - +0.8 VCC + 0.8 400 +40 V k
SWITCH CIRCUIT assert time de-assert time 100 80 - - 180 - ns ns
TTL INPUT PINS MUTE AND INV LOW-level input voltage HIGH-level input voltage input resistance input current positive logic; note 10 positive logic; note 10 referenced to GNDA V V k A
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RSSI and LOS detector PECL OR CML INPUT PINS IN AND INQ Vi(p-p) OS(red) Vio(cor) input voltage swing (peak-to-peak value) input offset reduction on-chip DC-offset compensation correction range low -3 dB cut-off frequency high -3 dB cut-off frequency dynamic range RSSI sensitivity 50 MHz, square; note 11 620 MHz, square; note 11 1.2 GHz, square; note 11 100 MB/s PRBS (231 - 1); note 11 1.2 GB/s PRBS (231 - 1); note 11 2.4 GB/s PRBS (231 - 1); note 11 TCsens LE temperature coefficient sensitivity linearity error see Fig.8; note 2 note 11 single-ended notes 2 and 4 peak-to-peak value; single-ended 0.4 25 -5 - 40 - 400 50 +5 mV dB mV
RSSI CIRCUIT f-3dB(l) f-3dB(h) DR SRSSI 0.5 1.5 57 10 10 9 9 10 10 -2 - 2.0 - - 0 referenced to GNDA 150 - internal output series resistance 3.5 1 2 60 12.5 12 11 12.5 12 12 0 0.5 2 2.5 63 15 14 13.5 15 14.5 14 +2 1 MHz GHz dB mV/dB mV/dB mV/dB mV/dB mV/dB mV/dB V/dBK dB
LOS DETECTOR hysLOS ta td Vi Ri Io(sink) Ro LOS hysteresis assert time de-assert time input signal waveform dependent note 2 note 2 3.0 - - - 350 - 5 4.0 5 5 dB s s V k
INPUT PIN LOSTH input voltage input resistance VCC 600
OUTPUT PIN LOS output sink current output resistance 1 6.5 mA k
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
SYMBOL OUTPUT PIN RSSI Vo Io
PARAMETER
CONDITIONS
MIN. VCC - 1.2 -1 - -
TYP.
MAX.
UNIT
output voltage output current
VCC +1
V mA
Band gap reference circuit OUTPUT PIN Vref Vref Cext Io(sink) Notes 1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 2. Guaranteed by design. 3. Minimum signal with limiting output. G AC 4. OS(red) = ---------G DC Vo 5. GV = ----Vi 6. Based on -3 dB cut-off frequency and rise/fall time. 7. Low limit can go as low as DC if the input signal overrides the input offset voltage correction range. 8. Vi = 100 mV (p-p) single-ended, Vo = 800 mV (p-p) single-ended. 9. Crosstalk of IC only. 10. When using a negative supply voltage, positive or negative logic can be used. The values will be different, see Fig.7. 11. Sensitivity depends on the waveform and is therefore a function of -3 dB cut-off frequency; see Section "RSSI and LOS detection", Equation (1). reference voltage allowed external capacitance output sink current VCC - 1.85 VCC - 1.6 - - - - VCC - 1.45 V 10 500 pF A
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
APPLICATION INFORMATION RF input and output connections Striplines, or microstrips, with an odd mode characteristic impedance of Zo = 50 have to be used for the differential RF connections on the PCB. This applies to both signal inputs and signal outputs. Each pair of lines should have the same length. Grounding and power supply decoupling The PCB ground connection has to be a large area of copper connected to a common ground plane with an inductance as low as possible.
TZA3014
To minimize low frequency switching noise in the vicinity of the TZA3014, the power supply line should be filtered once using a beaded capacitor circuit having a low cut-off frequency. The exposed die pad GNDp connection on the PCB must be a large area of copper to aid the transfer of heat from the IC to the PCB (see Figs 11 and 12).
2001 Jun 25
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Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
handbook, full pagewidth
0
1
2
3
4
5 mm
To central GND decoupling 0603
To central GND decoupling 0603
0603
0603
VCCA IN INQ VCCA
VCCB OUT OUTQ VCCB
0603
0603
0603
0603
0603
0603
0603
HTQFP cross-section
MGU134
In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 x 3 mm2 exposed die pad to a plane with maximum size. (2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes.
Fig.11 PCB layout for HTQFP package with positive supply voltage.
2001 Jun 25
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GND signal/GNDp
Boundary of 100 mm2 area
VCC VCC
24 23 22 21 20 19 18 17
MUTE 31
GNDA 32
INV
LOS
RSSI
GNDB 25
30
29
28
27
26
1 2 3 4 5 6 7 8 9 10 LOSTH 11 12 LEVEL 13 14 Vref 15 TEST 16
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
handbook, full pagewidth
0
1
2
3
4
5 mm
To central GND decoupling 0603
To central GND decoupling 0603
0603
0603
VCCA IN INQ VCCA
VCCB OUT OUTQ VCCB
0603
0603
0603
0603
0603
0603
0603
HTQFP cross-section
MGU136
In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 x 3 mm2 exposed die pad to a plane with maximum size. (2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes.
Fig.12 PCB layout for HTQFP package with negative supply voltage.
2001 Jun 25
20
GND signal/GNDp
Boundary of 100 mm2 area
VCC VCC
24 23 22 21 20 19 18 17
GNDA
GNDB
MUTE 31
INV
LOS
RSSI
32
30
29
28
27
26
25
1 2 3 4 5 6 7 8 9 10 LOSTH 11 12 LEVEL 13 14 Vref 15 TEST 16
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
BONDING PAD INFORMATION COORDINATES(1) SYMBOL VCCA IN INQ VCCA n.c. n.c. n.c. n.c. n.c. n.c. n.c. LOSTH n.c. n.c. LEVEL n.c. Vref n.c. TEST n.c. n.c. n.c. n.c. n.c. PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -928 -928 -928 -928 -928 -928 -928 -928 -928 -928 -707 -550 -393 -236 -79 +79 +236 +393 +550 +707 +928 +928 +928 +928 y +710 +553 +396 +239 +81 -81 -239 -396 -553 -710 -928 -928 -928 -928 -928 -928 -928 -928 -928 -928 -710 -553 -396 -239 n.c. n.c. VCCB OUTQ OUT VCCB GNDB n.c. n.c. RSSI LOS n.c. INV n.c. MUTE GNDA Note 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SYMBOL PAD x +928 +928 +928 +928 +928 +928 +707 +550 +393 +236 +79 -79 -236 -393 -550 -707
TZA3014
COORDINATES(1) y -81 +81 +239 +396 +553 +710 +928 +928 +928 +928 +928 +928 +928 +928 +928 +928
1. All x and y coordinates represent the position of the centre of the pad in m with respect to the centre of the die (see Fig.13).
2001 Jun 25
21
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
GNDA
40 39 38 37 36 35 34 33 32 31 VCCA IN INQ VCCA n.c. n.c. n.c. n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 x 0 0 y 30 29 28 27 26 25 24 23 VCCB OUT OUTQ VCCB n.c. n.c. n.c. n.c. n.c. n.c.
TZA3014U
GNDB 22 21 n.c.
MUTE
RSSI
handbook, full pagewidth
LOS
INV
n.c.
n.c.
n.c. n.c.
n.c.
LOSTH
n.c.
n.c.
LEVEL
TEST
n.c.
Vref
n.c.
MGU135
Fig.13 Bonding pad locations TZA3014U.
2001 Jun 25
22
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
PACKAGE OUTLINES HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm
TZA3014
SOT547-2
c y heathsink side X Dh 24 17 A ZE
25
16
e Eh wM bp Lp 32 pin 1 index 9 detail X 1 wM 8 ZD vM A L E HE A A2 A1 (A 3)
bp e D HD
B vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 5.1 4.9 Dh 3.1 2.7 E(1) 5.1 4.9 Eh 3.1 2.7 e 0.5 HD 7.1 6.9 HE 7.1 6.9 L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 0.89 0.61 0.89 0.61 7 0
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT547-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-06-15
2001 Jun 25
23
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
TZA3014
HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm
SOT560-1
D
xB b1 wM wM
ball A1 index area
b
E
b3 wM b2 detail X wM
xC B e C e1 vA
A y
e2
E1 e4
1 32 D1 e3 X A2 A 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. 0.80 A1 0.10 0.05 A2 0.70 0.60 b 0.35 0.20 b1 0.50 0.30 b2 0.50 0.35 b3 0.50 0.35 D 5.1 4.9 D1 3.2 3.0 E 5.1 4.9 E1 3.2 3.0 e 0.5 e1 4.2 e2 4.2 e3 4.15 e4 4.15 v 0.2 w 0.15 x 0.15 y 0.05 5 mm A1
OUTLINE VERSION SOT560-1
REFERENCES IEC JEDEC MO-217 EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-09-10 00-02-01
2001 Jun 25
24
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
TZA3014
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2001 Jun 25
25
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
Suitability of surface mount IC packages for wave and reflow soldering methods
TZA3014
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Jun 25
26
Philips Semiconductors
Product specification
2.5 Gbits/s postamplifier with level detector
DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
TZA3014
Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
2001 Jun 25
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001
Internet: http://www.semiconductors.philips.com
SCA 72
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/200/02/pp28
Date of release: 2001
Jun 25
Document order number:
9397 750 08203

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